1. Field of the Invention
This invention relates to a RAM (Random Access Memory) using a MOS FET (Metal Oxide Semiconductor Field Effect Transistor) and more particularly to a dynamic RAM consisting of one transistor/one capacitor memory cells.
2. Description of the Prior Art
Generally, when a random access memory (RAM) is formed on a semiconductor substrate, the areas occupied by the individual memory cells take up almost the whole area of the memory chip. In the latest MOS type semiconductor memory devices, in order to increase the memory capacity, what is known as the one transistor/one capacitor cell system has become the main trend and is being widely used. In this system, the area occupied by a single memory cell is small and the structure which consists of one transistor and one capacitor for each bit is simple.
As is well known this one transistor-one capacitor cell consists of a MOS transistor for reading out and writing in information and a capacitor connected in series between the MOS transistor and a power source for storing the information. Furthermore an address line is connected to a gate electrode of the MOS transistor and a digit line is connected to an electrode region of the MOS transistor. In this memory cell the reading out and writing in of information takes place by charging and discharging the capacitor controlling the MOS transistor. Conventionally this memory cell is formed as a semiconductor intregrated circuit as follows. A polycrystalline silicon gate electrode of the MOS transistor is formed bridging two diffused electrode regions, one of which is connected to the impurity diffused data line. An electrode of the capacitor made of polycrystalline silicon is formed adjacent to the MOS transistor on a semiconductor substrate with an insulating layer between this layer and the substrate. When the highest voltage is applied to the electrode of the capacitor, an inversion layer in the semiconductor substrate is formed, which works as both another electrode region of the MOS transistor and another electrode of the capacitor. Thereby a one transistor/one capacitor memory cell is formed. An address line made of aluminum disposed above an insulating layer is connected to the gate electrode at the contact portion.
The above-mentioned memory cell has some drawbacks. First, the MOS transistor is connected to the metal layer, which constitutes the address line, by the gate electrode, and one contact hole is needed per memory cell for electrical connection between this metal layer and the polycrystalline layer which constitutes this gate electrode. Therefore, as the memory capacity is increased, the number of contact holes on the semiconductor substrate also increases, which makes the chip size large. On the other hand, in order to make the integration density higher it is necessary to make the size of the contact holes more and more minute, and in this respect lowering of the manufacturing yield cannot be avoided. Also, a second drawback is that in the manufacture of the memory cell the gate electrode of the above-mentioned MOS transistor and one electrode of the capacitor are made in the same step. Specifically, a polycrystalline silicon layer is formed over the whole surface and then is etched away leaving two polycrystalline silicon electrodes. Accordingly, in order to make sure of separating the gate electrode of the MOS transistor and one electrode of the capacitor, the gap between the polycrystalline silicon layers must be at least about 5.mu.. This is the limiting value in the present state of separation etching by using a mask pattern, and the wasteful presence of such a space between the transistor and the capacitor, in addition to the first drawback, is still more undesirable as regards increasing the degree of integration.